The complexity of integrated circuits has dramatically increased during the last decade. System-on-chip and other multiple-core integrated circuits are being developed in order to support various applications such as but not limited to multimedia applications, real time applications and the like.
Modern integrated circuits are capable of executing a large amount of tasks substantially in parallel. Some of these tasks require to transfer relatively large amounts of data between memory mapped devices. Multiple channel Direct Memory Access (DMA) controller can manage multiple data transfers while reducing the load from the integrated circuit cores (processors). Nevertheless, DMA controllers can still load these cores by issuing an interrupt whenever certain DMA tasks are completed.
The following patents and patent applications, all being incorporated herein by reference, describe various DMA controllers: U.S. Pat. No. 6,738,881 of Olivier et al, U.S. Pat. No. 6,122,679 of Wunderlich, U.S. Pat. No. 5,450,551 of Amini et al., U.S. Pat. No. 6,728,795 of Farazmandnia et al., U.S. Pat. No. 4,502,117 of Kihara, U.S. Pat. No. 4,556,952 of Brewer et al., U.S. Pat. No. 5,838,993 of Riley at el., U.S. Pat. Nos. 5,692,216, 5,603,050 and 5,884,095 of Wolford et al., U.S. Pat. No. 6,298,396 of Loyer et al., U.S. Pat. No. 6,542,940 of Morrison et al., U.S. Pat. No. 6,041,060 of Leichty et al., U.S. patent applications Ser. No. 2004/0073721A1 of Goff et al, U.S. patent applications Ser. No. 20040037156A1 of Takashi et al., U.S. patent application publication number 2004021618A1 of Cheung, Japanese patent publication number JP07168741A2 of Hedeki et al., Japanese patent publication number JP06187284A2 of Masahiko, Japanese patent application publication number JP2004252533A2 of Yoshihiro, Japanese patent publication number JP04324755A2 of Tadayoshi et al., Japanese patent application publication number JP2004013395A2 of Hiroyuki, Japanese patent application publication number JP08249267A2 of Tetsuya, Japanese patent publication number JP02048757A2 of Katsuyuki et al., and PCT patent application publication number WO2005/013084 of Simon et al.
Due to the complexity of DMA tasks, and the large amount of DMA tasks developers spent many resources in defining the priority of each DMA task. These priorities can be tailored to specific programs.
There is a need to provide efficient devices and methods for controlling an execution of a DMA task.